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1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
ICS85222-02
GENERAL DESCRIPTION
The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-toIC S Differential HSTL translator and a member of the HiPerClockSTM HiPerClocksTM family of High Performance Clock Solutions from IDT. The ICS85222-02 has one single ended clock input. The single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to HSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.
FEATURES
* Two differential HSTL outputs * One LVCMOS/LVTTL clock input * CLK input can accept the following input levels: LVCMOS or LVTTL * Maximum output frequency: 350MHz * Part-to-part skew: 250ps (maximum) * Propagation delay: 1.25ns (maximum) * VOH: 1.4V (maximum) * Output crossover voltage: 0.68V - 0.9V * Full 3.3V operating supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free RoHS compliant packages
BLOCK DIAGRAM
Q0 CLK Pulldown nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nc GND
ICS85222-02
8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View
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ICS85222-02 1-TO-2, LVCMOS/LVTTL-TO-DIFFERENTIAL HSTL TRANSLATOR
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 Name Q0, nQ0 Q1, nQ1 GN D nc CLK Type Output Output Power Unused Input Description Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Power supply ground. No connect. Pulldown LVCMOS / LVTTL clock input.
Power Positive supply pin. 8 VDD NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 112.7C/W (0 lfpm)
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 50 Units V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK CL K VDD = VIN = 3.465V VDD = 3.465, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 Units V V A A
TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VOH VOL VOX VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Crossover Voltage Peak-to-Peak Output Voltage Swing Test Conditions Minimum 1.0 0 0.68 0.6 1.0 Typical Maximum 1.4 0.4 0.9 1.4 Units V V V V
NOTE 1: All outputs must be terminated with 50 to ground.
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD t sk(o) t sk(pp) tR / tF odc Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 3 Par t-to-Par t Skew; NOTE 4 Output Rise/Fall Time Output Duty Cycle 20% to 80% f 250MHz f > 250MHz 250 45 40 0.85 1.05 Test Conditions Minimum Typical Maximum 350 1.25 25 250 500 55 60 Units MHz ns ps ps ps %
% All outputs must be terminated with 50 to ground. NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
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PARAMETER MEASUREMENT INFORMATION
3.3V 5% PART 1 nQx
VDD
Qx
SCOPE
Qx PART 2 nQy
HSTL
nQx
Qy tsk(pp)
GND
0V NOTE: All outputs must be terminated with 50 to ground.
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
nQx Qx nQy Qy
VDD CLK nQ0, nQ1 Q0, Q1 tPD 2
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
nQ0, nQ1 Q0, Q1
80%
t PW
t
PERIOD
80% VSW I N G
Clock Outputs
20% tR tF
20%
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS:
HSTL OUTPUT All outputs must be terminated with 50 to ground.
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85222-02. In the example, the input is driven by a 7 ohm LVCMOS driver with a series termination. The decoupling capacitor should be physically located near the power pin. For ICS85222-02, the unused output need to be terminated.
Zo = 50 Ohm VDD=3.3V Q2 Ro ~ 7 Ohm Zo = 50 Ohm 5 6 7 8 U1 GND nc CLK VDD nQ1 Q1 nQ0 Q0 4 3 2 1 Zo = 50 Ohm + R1 50 R2 50 HSTL Input -
R6 Driv er_LVCMOS
43 ICS85222-02 VDD=3.3V C1 0.1u Zo = 50 Ohm
Zo = 50 Ohm + R3 50 R4 HSTL Input 50
FIGURE 2. ICS85222-02 HSTL BUFFER SCHEMATIC EXAMPLE
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85222-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85222-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW Power (outputs)MAX = 73.8mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 82.3mW = 164.6mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 164.6mW = 337.86mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total device power dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.337W * 103.3C/W = 104.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE JA
FOR
8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 1.
VDD
Q1
VOUT RL 50
FIGURE 1. HSTL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R ) * (V
L DD_MAX
-V
OH_MAX
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DD_MAX
-V
OL_MAX
Pd_H = (1.4V/50) * (3.465V - 1.4V) = 57.8mW Pd_L = (0.4V/50) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 82.3mW
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RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85222-02 is: 411
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PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUM 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85222AM-02 ICS85222AM-02T ICS85222AM-02LF ICS85222AM-02LFT Marking 85222A02 85222A02 5222A02L 5222A02L Package 8 Lead SOIC 8 Lead SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC Shipping Package tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET Rev A T1 B T2 T3B Table Page 5 6-7 1 2 2 3 Description of Change Added Schematic Example. Power Considerations - corrected power dissipation in calculations. Updated Block Diagram with Pulldown for CLK. Pin Description - changed pin 7 as Pulldown instead of Pullup. Changed note to reflect Pulldown. Pin Characteristics - changed Pullup Resistor to Pulldown. LVCMOS DC Characteristics Table - changed IIH from 5A max. to 150A max. and changed IIL from -150A min. to -5A min. Date 7/24/06
9/12/07
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